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nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 1 SP6339, sp6341 triple power supervisory circuit with manual reset and watchdog SP6339-sp6341 triple power supervisory c ircuit family is a family of microprocessor reset supervisory circuits with multiple reset voltages. the fam ily provides low voltage monitoring ability for up to three supplies with two precision factory-set thresholds and one user defined custom threshold. these circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. products in the family offer manual reset and watchdog functionalities. SP6339 and sp6341 are packaged in an 8-pin tsot package. all devices are fully specified over -40 o c to +85 o c temperature range. features low opera ting voltage of 1.6v low operating current of 20 a typical monitors up to 3 supplies simultaneously adjustable input monitors down to 0.5v reset asserted down to 0.9v 2% accuracy over temperature range open drain (od) or cmos rstb output 4 reset timeout periods: 50ms, 100ms, 200ms, and 400ms watch dog timer function -- wdi independent od or cmos watchdog output (active low) -- wdob manual reset input (active low) -- mrib 8 pin tsot package description now available in lead free packaging see page 2 for other available pinouts 1 2 3 4 5 6 7 8 8 pin tsot v2 SP6339 v1 wdi v3 mrib gnd wdob rstb open drain reset typical application circuit
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 2 absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifica - tions below is not implied. exposure to absolute maxi - mum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. terminal voltage (with respect to gnd) v1, v2.................................................... -0.3 to +6v open-drain rstb, wdob ..................................................... -0.3 to +6v cmos rst, rstb, wdob.... ...................................... . -0.3 to (v1+0.3v) feature and pinout diagram input current/output current...... ...........................,,.............. ..........20ma v3, mrib, wdi ........................ -0.3 to (v1+0.3v) operating temperature range ............................................... -4 0 c to +85 c storage temperature range...............................................-65 c to 150 c thermal resistance ja . .............................134 c/w part number v1 v2 v3 reset mrib wdi wdob SP6339 od active low od active low sp6341 cmos active low cmos active low 1 2 3 4 5 6 7 8 8 pin tsot v2 SP6339 v1 wdi v3 mrib gnd wdob rstb open drain reset 1 2 3 4 5 6 7 8 8 pin tsot v2 sp6341 v1 wdi v3 mrib gnd wdob rstb cmos reset representative samples available sipex product product description package v1 (volts) v2 (volts) v3 (volts) v4 (volts) reset (ms) ordering # SP6339 triple supervisor open drain low 8 pin tsot 4.625 2.313 0.5 n/a 200 SP6339ek1-l-z-j-c
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 3 electrical characteristics parameter min typ max units conditions operating voltage ran g e 0.9 5.5 v t a = -40oc to +85oc 20 30 ua v1 < 5.5v, v2 < 3.60v, all i/o pins open 15 25 v1 < 3.6v, v2 < 2.75v, all i/o pins open 4.532 4.625 4.718 z ( valid for v1 fallin g) 4.287 4.375 4.463 y ( valid for v1 fallin g) 3.013 3.075 3.137 x ( valid for v1 fallin g) 2.866 2.925 2.984 w ( valid for v1 fallin g) v1 reset 2.572 2.625 2.678 v ( valid for v1 fallin g) threshold 2.273 2.320 2.367 u ( valid for v1 fallin g) 2.146 2.190 2.234 t ( valid for v1 fallin g) 1.636 1.670 1.704 s ( valid for v1 fallin g) 1.548 1.580 1.612 r ( valid for v1 fallin g) 2.266 2.313 2.360 j ( valid for v2 fallin g) 2.144 2.188 2.232 i ( valid for v2 fallin g) 1.631 1.665 1.698 h ( valid for v2 fallin g) 1.543 1.575 1.607 g ( valid for v2 fallin g) v2 reset 1.360 1.388 1.416 f ( valid for v2 fallin g) threshold 1.286 1.313 1.340 e ( valid for v2 fallin g) 1.087 1.110 1.133 d ( valid for v2 fallin g) 1.029 1.050 1.071 c ( valid for v2 fallin g) 0.816 0.833 0.850 b ( valid for v2 fallin g) 0.772 0.788 0.804 a ( valid for v2 fallin g) threshold 1 tempco 0.06 mv/oc threshold 2 tempco 0.04 mv/oc threshold 1 h y steresis 0.65 % reference to vth1 typical threshold 2 h y steresis 0.5 % reference to vth2 typical v1 to rst/rstb dela y 50 us v1 = vth1 to (vth1-0.1v), vth1 = 3.075 v2 to rst/rstb dela y 50 us v2 = vth2 to (vth2-0.1v), vth2 = 1.575 reset timeout period ( t1 ) 37 50 63 ms topt-1 reset timeout period ( t2 ) 74 100 126 ms topt-2 reset timeout period ( t3 ) 148 200 252 ms topt-3 reset timeout period (t4) 296 400 504 ms topt-4 v v v1 = 1.6v to 5.5v; ta = -40oc to +85oc; unless otherwise noted. typical values are at ta =+25oc supply current
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 4 electrical characteristics parameter min typ max units conditions v3 in p ut threshold 490 500 510 mv v3 input current -50 50 na t a = +25oc v3 threshold h y steresis 1.5 mv mrib input threshold 0.4 v vil mrib input threshold 0.8*v1 v vih mrib minimum in p ut pulse width 1 us mrib glitch re j ection 150 ns mrib to rst/rstb dela y 100 ns mrib pull-up resistance 30 55 85 k? watchdog timeout period 1.2 1.6 2 sec wdi pulse width 0.1 us wdi input threshold 0.4 v vil wdi input threshold 0.8*v1 v vih wdi in p ut current -500 500 na wdi = 0.0v or v1 rstb (cmos or od) 0.4 v v1 = vth1 - 0.1v, isink = 1ma, out p ut asserted rstb (cmos) 0.8*v1 v v1 = vth1 + 0.1v, isource = 1ma, out p ut not asserted wdob (cmos or od) 0.4 v wdi = 0.0v or v1, v1 > vth1, v2 > vth2, v3 > 0.5, mrib float, isink = 1ma, wdob output asserted wdob (cmos) 0.8*v1 v v1 > vth1, v2 > vth2, v3 > 0.5, mrib float, wdob not asserted, isource = 1ma rstb / wdob output od leakage current 2 na t a = +25oc reset / watchdog outputs rstb / wdob wdi - watchdog input v1 = 1.6v to 5.5v; t a = -40oc to +85oc; unless otherwise noted. typical values are at t a =+25oc v3 reset comparator input mrib - manual reset input
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 5 pin description pin # name description 1 v1 first supply voltage input. also powers internal circuitry. trip threshold voltage internally set. 2 v2 second supply voltage input. trip threshold voltage internally set. 3 wdi watch-dog input pin. when no transition is detected at the wdi pin for the duration of wdi timeout period, reset is asserted. rstb output is used to signal watchdog timeout overflow -- rstb output pulses high/low (depending on the active reset polarity) for the reset timeout period after each watchdog timeout overflow. wdob remains at low logic level after watchdog timeout period is expired and it remains low until wdi makes a transition. rstb output is not affected by the watchdog functionality. the watchdog timer clears whenever the reset is asserted or manual reset is asserted or a transition is observed at wdi pin. 4 v3 input for the third supply voltage. trip threshold is 0.5v. 5 wdob watch dog output. open-drain or cmos, active low. if wdi remains at high or low logic level for longer than the watchdog timeout period, the internal watchdog timer overflows and wdob is asserted. wdob does not de-assert until the watchdog is cleared via transition at the wdi pin. another scenario for wdob to assert is when the reset output is asserted due to an under-voltage v1, v2, v3 condition. wdo de-asserts without a reset timeout period. floating wdi will not disable watchdog timer in devices with dedicated wdob output. open-drain wdob outputs require an external pull-up resistor. cmos outputs are referenced to v1. 6 gnd common ground reference pin. 7 mrib manual reset input pin. active low. it has an internal pull-up resistor. reset asserted when mrib is pulled low and is kept asserted for 200ms after mrib is released or pulled high. leave open if not used. 8 rstb reset output. open-drain or cmos, active low. reset is asserted when any of the three supply inputs is below its trip threshold. it stays asserted for 200 ms (typical / default) after the last supply input traverses its trip threshold. reset is guaranteed to be in the correct state for v1>0.9v. rstb asserts when v1 or v2 or v3 drop below their corresponding reset thresholds, or mrib is pulled low. rstb remains asserted for the reset timeout period after v1 and v2 and v3 exceed their corresponding reset thresholds or mrib goes low to high. open-drain outputs require an external pull-up resistor. cmos outputs are referenced to v1.
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 6 the SP6339 and sp6341 include a low- voltage precision bandgap reference, three precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed resistor divider chains and additional supporting circuitry. the family is designed to supervise up to 3 independent supply voltages. v1 and v2 supply inputs have their resistor dividers on the chip. their trip thresholds are factory trimmed. the v3 input allows users to customize an additional supply threshold to be monitored by means of an external resistor divider. the parts are furnished with manual reset and watchdog output functionalities. the watchdog functionality cannot be disabled. block diagram theory of operation osc wdi logic control logic v1 v2 v3 wdi rstb gnd 1.25v 0.5v mrib wdob band gap ref
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 7 figure 1: functionality of the SP6339 and sp6341. ? v1 > vth1, v2 > vth2 , and v3 > vth3 (all supplies over their corresponding thresh - olds)----> rstb is de-asserted after reset timeout period (trp) & wdob de-asserts immediately without waiting for reset timeout period. ? mrib goes to low to force reset ----> rstb is asserted immediately & wdob is not affected by mrib and is not asserted. ? wdi keeps making transitions within watchdog timeout period (t neither rstb nor wdob changes state. ? one of the supplies drops below its corresponding threshold (in this case v3) ----> rstb is asserted immediately & wdob is asserted immediately too. whenever v1, v2, v3 are below their specified thresholds wdob is asserted. theory of operation v1 v2 v3 vth1 vth2 vth3=0.5v mrib wdi rstb trp trp ttwd t nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corpora tion 8 v1 rstb resetb timeout period (400ms) application information SP6339watchdog timeout period v1 rstb wdi = gnd, v1=v2=v3=5v, mrib = open. watchdog timeout period = 1.52s
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 9 application information v1 and v2 glitch rejection v3glitch rejection v1 and v2 glitch rejection 0 50 100 150 200 250 0 20 40 60 80 100 120 overdrive (mv) d u r a t i o n ( u s ) rstb asserted above line v3 glitch rejection 0 20 40 60 80 100 120 0 20 40 60 80 100 120 overdrive (mv) d u r a t i o n ( u s ) rstb asserted above line
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 10 application information rstb vs. v1 (v2 = gnd) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v1 (vdc) r s t b ( v d c ) reset good reset timeout vs. temperature reset to (400ms) vs temperature 0 100 200 300 400 500 85 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 deg c t i m e o u t ( m s )
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 11 package: 8 pin tsot front view l ? gauge plane l2 c r r1 ? ? seating plane side view a a1 a2 seating plane d e e/2 e1 3 2 1 b e e1 e1/2 5 4 pin1 designator to be within this index area (d/2 x e1/2) top view (l1) d/2 8 7 6 min nom max min nom max a - - 1.10 - - 0.043 a1 0.00 - 0.10 0.000 - 0.004 a2 0.70 0.90 1.00 0.028 0.036 0.039 c 0.08 - 0.20 0.003 - 0.008 d e e1 l 0.30 0.45 0.60 0.012 0.018 0.024 l1 l2 0? 4 8? 0? 4? 8 1 4? 10? 12? 4? 10? 12 r 0.10 - - 0.004 - - r1 0.10 - 0.25 0.004 - 0.010 b 0.22 - 0.38 0.009 - 0.015 e e1 1.95 bsc 0.60 ref 0.024 ref 1.60 bsc 0.063 bsc 0.077 bsc 0.65 bsc 0.026 bsc 0.25 bsc 0.010 bsc sipex pkg signoff date/rev: jl oct3-05 / rev a symbol 8 pin tsot jedec mo-193 variation ba 2.90 bsc 0.114 bsc 2.80 bsc 0.110 bsc dimensions in millimeters: controlling dimension dimensions in inches conversion factor: 1 inch = 25.40 mm
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 12 part naming nomenclature sp63nn - th1 - th2 - topt t1 -- 50 ms t2 -- 100 ms t3 -- 200 ms t4 -- 400 ms a -- 0.788 v b -- 0.833 v c -- 1.050 v d -- 1.110 v e -- 1.313 v f -- 1.388 v g -- 1.575 v h -- 1.665 v i -- 2.188 v j -- 2.313 v z -- 4.625 v y -- 4.375 v x -- 3.075 v w -- 2.925 v v -- 2.625 v u -- 2.320 v t -- 2.190 v s -- 1.670 v r -- 1.580 v 30 -- quad sp, mr, wdi, od rstb 31 -- quad sp, od rstb 32 -- quad sp, mr, wdi, cmos rstb 33 -- quad sp, cmos rstb 34 -- quad sp, mr, wdi, cmos rst 35 -- quad sp, cmos rst 36 -- triple sp, wdi, pf, od rstb 37 -- triple sp, wdi, pf, cmos rstb 38 -- triple sp, wdi, pf, cmos rst 39 -- triple sp, mr, wdi, od rstb - wdob 40 -- dual sp, wdi, od rstb - wdob 41 -- triple sp, wdi, pf, cmos rstb - wdob 42 -- dual sp, wdi, cmos rstb - wdob { { { a b c d e f g h i j k l m a b c d example: jzjd means: SP6339 in tsot-8 lead package v1 threshold is 4.625v v2 threshold is 2.313v reset timeout is 400ms jzjd pin 1
nov 20-06 rev j SP6339-sp6341 triple power supervisory circuit ? copyright 2006 sipex corporation 13 ordering information model temperature range package type SP6339ek1-l-x-x-x.......................................-40 c to +85 c................................lead free 8-pin tsot SP6339ek1-l-x-x-x/tr.................................-40 c to +85 c................................lead free 8-pin tsot sp6341ek1-l-x-x-x........................................-40 c to +85 c................................lead free 8-pin tsot sp6341ek1-l-x-x-x/tr..................................-40 c to +85 c................................lead free 8-pin tsot available in lead free packaging only. /tr = tape and reel pack quantity 2,500 for tsot. contact factory for availability of particular voltage threshold and reset timeout options. note that the ordering information denoting those options corresponds to the part naming nomenclature shown on the previous page. ordering example: SP6339ek1-l-w-g-c/tr == w -- 2.925v for voltage threshold 1; g -- 1.575v for voltage threshold 2; and c -- 200ms reset timeout. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

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